1. Field of the Invention
The present invention relates to a touch-sensing input device and more particularly, to a method to prevent loss of data of a transistor-based memory unit is achieved by: erasing the floating gate (FG) and injecting a small amount of electrons into the floating gate (FG) to avoid electron accumulation in the first tunnel oxide (TO) and the second tunnel oxide (TO) and to allow normal data access to the floating gate (FG), and then using an electric field of a normal write to inject electrons in the floating gate (FG) to prevent channel conduction between the source (S) and the drain (D) and to allow writing data into the floating gate (FG), thereby reducing the possibility of a read error.
2. Description of the Related Art
A memory is a semiconductor component for storing electronic information or data, etc. Semiconductor memory devices made by using a semiconductor manufacturing process can be classified into non-volatile semiconductor devices (such as flash memory device) and volatile semiconductor devices [such as dynamic random access memory (DRAM), static random access memory device (SRAM), etc.]. A flash memory is a non-volatile semiconductor memory that does not require power to retain data and, that can be electrically erased and reprogrammed. For the advantages stated, flash memory devices are widely used in mobile electronic devices, such as tablet computers, smart phones, digital cameras, PDAs, or other mobile game devices.
A flash memory erases data in units called blocks. Every memory block comprises a plurality of memory cells. A basic flash memory cell consists of a storage transistor with a control gate (CG), a floating gate (FG), a source (S) and a drain (D). The memory cell information is based on the amount of electrons stored in the floating gate (FG). Normally, an erase operation is performed before a write operation, i.e. before electrons are injected into the floating gate (FG). When the floating gate (FG) has sufficient electrons, an electric field effect is created in the floating gate (FG) to prevent the formation of the D-S channel between the source (S) and the drain (D). When the flash memory is read, only a small current (leakage current) or no current is measured, representing state “0” or a logic “0”. When the floating gate (FG) does not have enough electrons to prevent the formation of the D-S channel between the source (S) and the drain (D), the D-S channel between the source (S) and the drain (D) conducts. Thus, when the flash memory is read, a large enough current (VGS>Vth) is measured, representing state “1” or a logic “1”.
If defects occur in the manufacturing process, hot electrons may get stuck in the tunnel oxide (TO) between the floating gate (FG) and the control gate (CG) over time, and the electrons will continue to accumulate in the tunnel oxide (TO), such that when the flash memory is read, the D-S channel between the drain (D) and the source (S) may not be formed. Even when the floating gate (FG) does not have enough electrons to prevent the formation of the D-S channel between the drain (D) and the source (S), which should result in state “1” or a logic “1”, the electrons accumulated in the tunnel oxide (TO) would cause an incorrect state “0” or a logic “0” to be read as a result. Thus, when writing new memory cell information into the floating gate (FG), it will be overlapped on the original memory cell information, resulting in loss of memory data.
Therefore, it is desirable to provide a method to overcome the aforementioned problem of loss of data of the floating gate due to accumulation of electrons in the tunnel oxide layer.